This application is based upon and claims priority of Japanese Patent Application No. 2000-266266, filed on Sep. 1, 2000, the contents being incorporated herein by reference.
1. Field of the Invention
This invention relates to formation of a low temperature silicon nitride film, which can be applied for the interlayer insulation film of LSI, for instance.
Since the stray capacitance between two wirings being apart from each other increases if the dielectric constant of the insulating layer is high, it becomes an obstacle in high-speed operation of the device when plural wirings are structured in a multi layer, placing the insulation layer between the wiring layers, stacking one by one, and thereby forming a semiconductor device. Nowadays, it becomes remarkable that the stray capacitance between wirings can be lowered by lowering the dielectric constant of the insulation film material between such layers as much as possible because the insulation film between layers cannot be so thickened along with making of the entire semiconductor device smaller and more integrated, and thereby, trying to obtain higher operating speed performance of the device. At the same time, because recent highly integrated semiconductor devices are desired to be processed in a much lower temperature compared with the conventional process, a lower temperature formation of the interlayer insulating film has been highly demanded recently.
2. Discussion of the Related Art
In accordance with recent developments of higher integration of Large Scale Integration Circuit (LSI), even a semiconductor device element of less than 0.2 xcexcm minute size is now integrated in the Si substrate surface. LSI can obtain its function by connecting between the semiconductor device elements through wirings. However, if wirings are arranged to make a detour in order to avoid forming unwanted cross-sections with other wirings, then wirings will occupy a large part of the chip surface, and moreover, such long wirings will raise unwanted signal delays. Then, it has been commonly applied that wirings are arranged in a multilayer structure so as to connect with each other up and down through an interlayer insulating film between them. FIG. 1 illustrates a cross-sectional view of a multilayer wiring structure.
Insulation film 1631 is formed on a silicon substrate 161, and the contacting plug is formed inside an opening through the insulation film 1631 so that a first wiring 1651 is electrically connected with device formation region 162. In addition, a second connection is formed between the first wiring 1651 and a second wiring 1652 through a via plug, which is buried in a via hole 1661 opening in an insulation film 1632, and a third connection is formed between the second wiring 1652 and a third wiring 1653 through a via plug, which is buried in a via hole 1662 opening in an insulation film 1633. In accordance with the same manner as aforementioned repeatedly in several times, a multilayer wiring structure will be accomplished, and such multilayer formation process will be finalized by covering the uppermost wiring by depositing sealing film 167.
However, because the multilayer wiring structure is comprised of thin insulation films between wirings, stray capacitance will significantly appear, and it will therefore cause the wiring delay. Also, crosstalk can be caused when each of two high frequency signals flows through each of two wirings isolated by the interlayer insulating film with each other respectively, and thereby misoperation will frequently occur. Such crosstalk problems or signal delays will be prevented if only the interlayer insulating film is formed thick enough to keep a distance between wirings. However, on the other hand, if the interlayer insulating film is thickly formed then it is necessary to deeply open a contact hole or via hole. The formation of a deep contact hole or a deep via hole through such a thick interlayer insulating film should make an opening step more difficult. From the above point of view, the interlayer insulating film should be thinner rather than thicker. For the new generation device later than 256 Mbit DRAM (Dynamic Random Access Memory), a contact hole diameter will be smaller than 0.25 xcexcm than before along with the development of higher integration. However, for making the opening by dry etching easy, an aspect ratio, namely a ratio between contact hole depth and contact hole diameter, should be no more than 5. If the contact hole diameter should be less than 0.25 xcexcm and the aspect ratio should be less than 5, then the thickness of the interlayer insulating film is to be as thin as less than 1 xcexcm.
Meanwhile, as likely as the aforementioned problem between upper and lower wiring layers, the stray capacitance problem might be seriously occurred even between two wirings adjacent to each other disposed on the same interlayer insulating film. This is because, according to miniaturization of the semiconductor device, the distance between wirings as well as the width of such wirings will be shortened. In the near future, inevitably the width of the wiring could be less than 0.25 xcexcm. It is highly demanded that the wiring intervals should not be expanded because of such miniaturized semiconductor device""s super-high integration.
To solve the problem between upper and lower wirings, there is room for doing the effort to thicken the insulation film between interlayer insulating films as much as possible. However, as the function of the circuit is complicated, there becomes no room for designing around, and thus the problem between plural wirings on the same interlayer insulating film will be more serious than the problem between upper and lower wirings.
When the circuit is designed, distribution constant circuit handling is necessary either in the case of the same level wirings or in the case of upper and lower wirings to accurately understand the wiring delay according to the increase of the capacitance between the wirings decided by interlayer insulating film thickness and crosstalk.
FIG. 2 shows the capacitance for each unit wiring length between the wiring layer and the silicon substrate wiring insulated by silicon oxide film of H in thickness (relative dielectric constant 3.9) from which R. L. M. Dang are shown on volume EDL-2 and page 196 of IEEEE Electron Device Letters in 1981. It is shown as the width W of wiring decreases that actual capacitance C greatly increases by a so-called fringe effect compared with the capacitance calculated by the parallel plate electrode approximation. Moreover, when height T of wiring is large at the same time, it is understood that capacitance C increases more and more.
Moreover, according to FIG. 3, which is shown in the above reference, total capacitance Cf per unit length between wiring and silicon substrate should be increased along with miniaturization of its wiring intervals only if wiring width W/wiring thickness H exceeds one, because the capacitance C12 between two wirings isolating so as to have wiring interval S is increased nevertheless capacitance C11 between wiring and silicon substrate is decreased. That is, each of the device elements could be highly operatable if the device is highly integrated and miniaturized, however, the wiring resistance and stray capacity generally increase if each of inter-element wirings is also highly integrated and miniaturized. As a result, operation speed as the entire LSI will not rise at all.
The result of FIGS. 2 and 3 is an analytical result concerning the stray capacitance between wiring and the silicon substrate, which are isolated from each other by an interlayer insulating film. Strictly to say, this is not the same result as the stray capacitance between upper and lower wirings. However, circumstances are substantially the same for the stray capacitance between the wiring layers. For instance, Japanese Laid-Open Patent Specification Hei 10-223625 discloses such a problem. Now, the development of new material, which is well applicable to interlayer insulating film even in highly integrated semiconductor devices, is highly demanded as a substitute for conventional silicon nitride film of the relative dielectric constant 7 or silicon oxide film of the relative dielectric constant 3.9, under the aforementioned technical background.
Especially, the silicon nitride film is broadly applied to insulation film between layers as a diffusion barrier layer or an etching stop layer or between wiring materials. Thus, M.Tanaka et al. disclosed a new approach to develop an insulating material of smaller relative dielectric constant at International Symposium on VLSI Technology 1999. Such new insulating material disclosed at that Symposium is amorphous silicon nitride chloride film (SiNCl), in which the dielectric constant can be decreased to even less than 5.4.
Although the aforementioned SiNCl (amorphous silicon nitride chloride) film seems to be effective in such low dielectric constant at present, the relative dielectric constant should greatly still decrease further compared with conventional silicon oxide or other well-known insulating materials. Also, SiNCl film formation needs rare gas as a raw material, and therefore film formation cost could be raised compared with conventional film formation to which common SiH4 is applied. In addition, Si2Cl6 liquefies easily and there are difficult handling problems among use of Si2Cl6 and NH3 as a raw material gas at SiNCl film formation.
Moreover, the adoption of copper (Cu) or copper (Cu) alloy wiring material might become a major trend replacing the aluminum wiring material in the future as a more miniaturized semiconductor device besides the above-mentioned problem. This is because in order to lower the wiring resistance which has become noticeable as the wiring layer becomes finer, it has become necessary to use wiring material with lower resistance. Copper (Cu) is comparatively difficult to handle in the process of the semiconductor device, and when it is adopted, it requires new solutions of problems. One of the problems is known that if copper is simply placed directly contacting an interlayer insulating film such as a silicon oxide film, the copper diffuses into the interlayer insulating film due to the heat during the process. In order to solve this problem, it is necessary to form a diffusion barrier so that the wiring layer and silicon oxide film are separated and do not contact each other. Therefore, it is desirable that the insulation film has a high barrier performance against copper diffusion for a very-highly-integrated future device, which inevitably will adopt copper (Cu) or copper alloy wiring material.
This invention provides a solution for the aforementioned problems of the prior art and is to develop a new desirable silicon nitride film formation technology, which is suitable for a very-large-scale-integrated semiconductor device. More specifically, the silicon nitride film with lower relative dielectric constant suitable for interlayer insulating film can be obtained from SiH4 and NH3 without using a special gas. Especially, in a miniaturized semiconductor device where wiring material contains copper, the diffusion control ability of copper is improved as a secondary effect, and thus it is generally applicable to the fabrication process for a highly miniaturized semiconductor device. In general, the problem to be solved by the present invention is to establish a desirable silicon nitride film formation technology of the very-large-scale integrated semiconductor device.
As a solution against such related art""s problem, each of the following inventions, for instance, can be applied according to the present invention.
(1) A first aspect is a silicon nitride film comprising a ratio of N: Si of from 1.0-1.1:1 and a ratio of O: Si of from 0.1-0.15:1, and being formed through catalytic CVD method using monosilane and ammonia, and having a relative dielectric constant of 6 or less. Here, the catalytic CVD method can be carried out using at least one catalyst selected from the group consisting of tungsten, platinum, palladium, molybdenum, silicon, alumina, silicon carbide, a metallic-deposited ceramics, tantalum, titanium, titanium oxide, and vanadium. A heating resistance can be applied to the catalyst.
According to the first aspect, a silicon nitride film with a low dielectric constant of 6 or less is obtained easily and at low cost by using common gases of SiH4 and NH3.
(2) A second aspect is a semiconductor device having the silicon nitride film of (1) at least in part of the insulating layer.
(3) A third aspect is a semiconductor device having the silicon nitride film of above (1) at least in part of the interlayer insulating layer in the multilayer structure.
(4) A fourth aspect is a semiconductor device comprising an interlayer insulating layer of said silicon nitride film as in each of the above between copper-including layers.
(5) A fifth aspect is a semiconductor device having: a silicon nitride film described in above (1) covering a lower wiring layer; and a planarized insulating layer of one member selected from the group consisting of silicon oxide, silicon oxynitride, FSG (fluorosilicate glass), BPSG (boro phosphosilicate glass), PSG (phosphosilicate glass), and USG (undoped silicate glass) covering the silicon nitride film.
(6) A sixth aspect is a method for fabricating a semiconductor device, comprising the steps of: forming an interlayer insulating layer of silicon nitride film of above (1); depositing a film selected from at least one material selected from the group consisting of silicon oxide, silicon oxynitride, FSG (fluoro silicate glass), BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), and USG (undoped silicate glass); and forming a planarized insulating film by polishing the surface of said film.
In the method for fabricating a semiconductor device as in the above, the interlayer insulating film formation step through the catalytic CVD method can be performed by controlling a substrate holder temperature over 150xc2x0 C.
As to advantageous effects of the present invention, there is an effect that silicon nitride film, which is broadly applicable to the miniaturized or large-scale integrated semiconductor devices, can be easily formed by using commonly used gases according to the present invention. More specifically, the silicon nitride film is desirable for the use in the miniaturized or super large-scale integrated semiconductor device in the following two viewpoints.
First, a new silicon nitride film of lower dielectric constant can be formed from common gas under low temperature. Therefore, the new silicon nitride film of the present invention is applicable to an interlayer insulating film between wirings inside the miniaturized semiconductor device. That is, the present invention is favorably applicable to the fabricating process for forming the miniaturized or very large-scale integrated semiconductor devices. In the related art, the high dielectric constant of the interlayer insulating film has prevented the device from high-speed operation. Further, long time heating process badly influences the other device formation areas on the same substrate during the formation step of the interlayer insulating film if not through low temperature formation process, and thereby, the device characteristic would be degraded. Otherwise, yield ratio in final product quality would be critically worsened. However, the present invention will solve at once all of the above. Moreover, because very common gas can be used, the advantage on the manufacturing cost side can be acquired.
In addition, according to the present invention, the effect of preventing copper (Cu) diffusion is much better than common silicon nitride, and thus it is favorably combined with a copper (Cu) containing wiring layer. Each of wiring layers are becoming to be very fine in the highly miniaturized recent device, and thereby wiring layer resistance would become a significant problem even by using aluminum-alloy. In such a situation, conventional wiring material, i.e., aluminum or aluminum alloy must be replaced by copper (Cu) or copper (Cu) alloy for the next generation devices. The new silicon nitride film (SiN) of the present invention is particularly favorable for the miniaturized or super highly integrated devices employing such copper containing wirings.
FIG. 1 is a cross-sectional view of the multi-layer wiring structure according to the related art.
FIG. 2 is an explanatory figure (No. 1) of the stray capacitance analysis result between the wiring layers.
FIG. 3 is an explanatory figure (No. 2) of the stray capacitance analysis result between the wiring layers.
FIG. 4 is a cross-sectional view of a catalyst CVD apparatus according to the embodiment of the present invention.
FIG. 5 is an upper view of catalyst CVD apparatus chamber according to the embodiment of the present invention.
FIG. 6 is an explanatory figure illustrating the correlation of the relative dielectric constant and the temperature of the substrate holder.
FIG. 7 is an explanatory figure illustrating the relation to the composition ratio in the direction of depth of the temperature of the substrate holder and the silicon nitride film (in case of 100xc2x0 C. temperature of the substrate holder).
FIG. 8 is an explanatory figure illustrating the relation to the composition ratio in the direction of depth of the temperature of the substrate holder and the silicon nitride film (in case of 400xc2x0 C. temperature of the substrate holder).
FIG. 9 is an explanatory figure illustrating the etching rate which uses the buffered hydrofluoride acid solution which is called 16BHF.
FIG. 10 is an explanatory figure (No. 1) illustrating the result of investigating the temperature change in the surface of the silicon substrate by the difference of setting the temperature of the substrate holder.
FIG. 11 is an explanatory figure (No. 2) illustrating the result of investigating the temperature change in the surface of the silicon substrate by the difference of setting the temperature of the substrate holder.
FIG. 12 is an explanatory figure illustrating the result of the Bias and Temperature (BT) stress test.
FIG. 13 is a cross-sectional view of the semiconductor device according to one embodiment of the present invention.